1. Field of the Invention
The present invention relates generally to semiconductor packaging and more specifically to multichip semiconductor packaging.
2. Description of the Related Art
In an effort to produce smaller and lighter electrical devices there is a continuing effort to reduce the size of semiconductor components. Stacking multiple chips into a single package is one technique for reducing the footprint required for semiconductor devices.
There are several methods of designing a stacked package. FIG. 1 is a diagrammatic cross sectional view of a common multichip package 100. Two dice 105 and 110 are each electrically connected to a substrate 115 via wire bonding 120 and 125. Each die 105 and 110 has an exclusive electrical link to the substrate 115. The multichip package 100 is arranged as a ball grid array (“BGA”), a type of package in which the input and output points are solder bumps arranged in a grid pattern.
FIG. 2 is a diagrammatic cross sectional view of another multichip package 200. A daughter die 205 is directly connected to a mother die 210 via wire bonding 215. Both the daughter die 205 and the mother die 210 are also connected directly to the substrate 220 via wire bonding 225 and 230.
Although the described packages work well in many applications, there are continuing efforts to further improve multichip packages.